The present invention relates generally to non-volatile memory devices and, more particularly, to methods and systems for optimization of layout density in a periphery area using a three-metal interconnection process in flash electrically erasable programmable read-only memory (EEPROM) devices.
Flash memories are popular memory storage devices because they store information in the absence of continuous power and are capable of being constructed in a very compact form. Flash memory is typically constructed by fabricating a plurality of electrical components in a silicon substrate. It is desirable to place as many of the electrical components as possible in the available area on the silicon substrate to optimize functionality and economical manufacture. The density or layout area of the electrical components depends on the physical size of the electrical components and the electrical connections between components. As the size of the electrical components decreases due to technological advances, more components can be placed in the available area on the flash memory. However, more electrical components require more electrical connections that can offset the layout area gained by the smaller component size.
Flash memory devices include two functional areas, a core cell area to perform memory functions and a periphery area to perform logic functions. As known in the art, the core cell area includes rows and columns of electrical components that are floating-gate transistors formed in the silicon substrate during fabrication. The floating-gate transistors located in the core cell area of the flash memory are typically referred to as core memory cells. The rows of core memory cells within the core cell area are typically electrically connected to form wordlines and the columns of core memory cells within the core cell area are typically electrically connected to form bitlines. As known in the art, the wordlines and bitlines are used to provide predetermined operational voltages to erase, read and write the core memory cells within the core cell area.
In addition to the core cell area, the flash memory also has a periphery area that includes a plurality of electrical components such as transistors, resistors, capacitors and diodes formed in the silicon substrate during fabrication. As known in the art, the resistors, capacitors and diodes may be formed during fabrication to create electrical components such as bipolar and field-effect transistors. The electrical components are electrically connected to form integrated circuits that perform logic functions within the flash memory to support operations such as the read, write and erase of the core memory cells. Part of the formation of the electrical connections of the electrical components occurs during a fabrication process known in the art as metallization.
Generally, metallization involves depositing a thin film of conductive metal on the flash memory such that the electrical components are formed and electrically connected with the conductive metal. In addition to forming portions of the electrical components, the conductive metal electrically connects the electrical components in a predetermined configuration, thereby xe2x80x9cwiringxe2x80x9d the electrical components to create the integrated circuits. The conductive metal that electrically connects the electrical components is routed on the flash memory and contributes to the layout area consumed.
Known prior art flash memory uses a two-metal layer metallization process to electrically connect the electrical components in the periphery area of the flash memory. A first layer of metal is typically used to form portions of the electrical components and to electrically connect the electrical components to form a plurality of sub-circuits that perform predetermined logic functions during operation. A second layer of metal is typically used to electrically connect one sub-circuit with another and to electrically connect the sub-circuits with the core memory cells in the core area such that operations can be performed within the flash memory.
A known problem with this method and system of electrical connection is layout area consumed by routing channels of the first and second layer of metal between the sub-circuits in the periphery area. In addition, layout area is consumed for routing channels that are used to route the first and second metal layers between the electrical components that form the sub-circuits. The layout area for the routing channels required by existing electrical connection systems and methods increases the size of the periphery area on the flash memory. The area on the flash memory that is not consumed by the periphery area can be reserved for the core cell area, allowing more core memory cells to be fabricated on the flash memory. It is therefore desirable to minimize the amount of periphery area consumed, thereby increasing the amount of information stored in the flash memory. That is, the ratio of the core area to the periphery area can be maximized.
To that end, a need exists for flash memory with an improved method and system of interconnection of electrical components to minimize the area consumed in the periphery area of the flash memory.
The present invention discloses a method and system of optimizing layout area consumed in a periphery area of a flash memory. The flash memory includes a core cell area and the periphery area. Within the core cell area, the flash memory includes a plurality of core memory cells; and, within the periphery area, the flash memory includes a plurality of sub-circuits. Generally, the core cell area provides memory-related functions in the flash memory and the periphery area supports the memory-related functions by providing logic-related functions in the flash memory.
The core cell area and the periphery area share the available area on the flash memory. As such, a smaller periphery area is desirable, thereby increasing the area available for the core cell area. In the preferred embodiment, selectively placing and electrically connecting a plurality of electrical components to form the sub-circuits and selectively electrically connecting the sub-circuits with the core memory cells mininimizes the layout area of the sub-circuits in the periphery area.
The preferred sub-circuits include the electrical components such as transistors, resistors, capacitors and diodes that are electrically connected with a first metal layer, a second metal layer and a third metal layer. The electrical components are electrically connected to form the sub-circuits by the first metal layer and the second metal layer. The sub-circuits are electrically interconnected with each other and with the core memory cells in the core cell area by the third metal layer. Those skilled in the art would understand that, typically, the majority of electrical components in the periphery area used to create the integrated circuits are transistors; however, other electrical components such as diodes and resistors could also be utilized.
The circuit layout of the sub-circuits is such that the transistors are oriented to form a plurality of rows of transistors wherein each transistor has a drain and a source oriented along an axis parallel with the rows of transistors. In another preferred embodiment of the present invention, the drain and the source of the transistors are not oriented along an axis parallel with the rows of transistors.
The first metal layer is applied to the periphery area of the flash memory during fabrication to form and partially interconnect the electrical components in a predetermined circuit configuration. The first metal layer comprises a plurality of first metal lines that provide interconnecting surface xe2x80x9cwiringxe2x80x9d for the predetermined circuit configuration. The layout in the periphery area of the first metal lines is oriented to extend along an axis substantially parallel to the rows of transistors. The second metal layer also provides surface xe2x80x9cwiringxe2x80x9d of the electrical components to complete the predetermined circuit configuration and form the sub-circuits. The second metal layer is also applied to the periphery area of the flash memory during fabrication. The layout of the second metal layer on the flash memory is deposited to form a plurality of second metal lines that are oriented to extend along an axis substantially perpendicular to the first metal lines.
The sub-circuits are selectively electrically interconnected and electrically connected with the core memory cells in the core cell area by the third metal layer. The third metal layer is also applied to the periphery area of the flash memory during the fabrication process and is adapted to form a plurality of third metal lines. The third metal lines provide surface xe2x80x9cwiringxe2x80x9d to electrically connect the sub-circuits with the core memory cells and are oriented to extend along an axis substantially parallel to the first metal lines.
During the fabrication process, the periphery area consumed by the transistors, the first metal layer, the second metal layer and the third metal layer is optimized in the preferred embodiment. The orientation of the transistors uniformly in rows allows the spacing between the transistors in the rows to be minimized without causing short circuits or undesirable leakage currents while still allowing electrical connection of the transistors. In addition, the combination of the first metal layer and the second metal layer to form and electrically connect the electrical components to create the sub-circuits also minimizes the periphery area consumed.
The electrical connections with the transistors are typically located directly below the first metal lines of the first metal layer. Since the first metal lines are substantially straight, additional spacing between the rows of transistors to allow for electrical connection of the transistors to the first metal layer is minimized. The second metal lines of the second metal layer provide additional electrical connections to complete the sub-circuits, thereby minimizing bends in the first metal lines and repositioning of the electrical components under the first metal lines. The second metal lines are also substantially straight and orthogonally pass over the first metal lines, thereby minimizing noise and allowing efficient electrical connections that further minimize consumption of the periphery area. The third metal layer provides electrical connection of the first metal layer and the second metal layer with the core memory cells. As such, the third metal lines can be substantially straight and be routed on top of the sub-circuits such that consumption of the periphery area is minimized.
These and other features and advantages of the invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.